Conditional clock buffer circuit

ABSTRACT

A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.

This application is a continuation of U.S. patent application Ser. No. 10/136,109, filed on May 1, 2002, now U.S. Pat. No. 6,535,036, which is a continuation of U.S. patent application Ser. No. 09/961,611, now U.S. Pat. No. 6,411,152, filed on Sep. 24, 2001.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to electronic circuits, and more particularly, to clock buffer circuits.

2. Description of the Related Art

As electronic circuits increase in density, particularly integrated circuits, power consumption has also increased. In order to minimize power consumption, power management circuitry may be used. Power management circuitry may be used to selectively and/or temporarily remove power from a certain part of an electronic circuit during times while that part is inactive. Alternatively or in addition, conditional clocking schemes may be used.

Conditional clocking may be used to conditionally generate a clock signal to a functional circuit dependent on whether or not the functional circuit is active. If the circuit is active, the clock signal is generated (e.g. rising and falling edges are generated providing a high phase and a low phase of the clock signal). If the circuit is inactive, the clock signal may be inhibited (e.g. held in a constant state instead of toggling high and low). Inhibiting the clock signal during idle times for the functional circuit may result in power savings since the state of the circuit is held steady and thus the circuit may experience minimal switching activity. Typically, the condition input to the conditional clock circuitry (which determines whether the clock signal is generated or inhibited) has a relatively high setup time with regard to an input clock edge, to ensure glitch free operation of the conditional clock signal.

SUMMARY OF THE INVENTION

A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit configured to precharge a first node and a second node, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, respectively, and a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.

In one embodiment, the clock buffer circuit may be configured to drive a clock signal to functional logic. Power management for the functional logic may be controlled by conditional clocking from the clock buffer circuit. The clock buffer circuit may include a condition input. When a certain condition is asserted on the condition input, the clock buffer circuit may prevent transitions of the output clock signal. This may result in reduced power consumption by the functional logic receiving the output clock signal. When the condition which caused the circuit to inhibit the output clock signal is removed, the clock buffer circuit may once again begin driving the output clock signal to the functional logic.

Thus, in various embodiments, the conditional clock buffer circuit may be used to provide conditional clocking to various logic circuits. The conditional clock buffer circuit may be used in providing fine-grain power management functions to a chip.

BRIEF DESCRIPTION OF THE DRAWINGS

Other aspects of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

FIG. 1 is a block diagram of a system in which one embodiment of a clock buffer circuit may be implemented;

FIG. 2 is a schematic diagram of one embodiment of a clock buffer circuit;

FIG. 3 is a timing diagram illustrating the operation of one embodiment of a clock buffer circuit; and

FIG. 4 is a block diagram of one embodiment of a carrier medium.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will hereby be described in detail. It should be understood, however, that the drawings and description thereto are not intended to limit the invention to the particular form disclosed, but, on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling with the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Turning now to FIG. 1, a block diagram of a circuit in which one embodiment of a clock buffer circuit 120 may be implemented is shown. In the embodiment shown, clock buffer circuit 120 is a conditional clock buffer circuit, and is configured to receive an input clock signal, Clk, and drive an output clock signal, Clk_out, to functional logic 105. Functional logic 105 may be any type of clocked logic circuit. In various embodiment, functional logic 105 may be an integrated circuit, or a portion of an integrated circuit. Some integrated circuits may include a plurality of clock buffers 120, each having an associated conditional logic 110 and an associated functional logic 105. Employing multiple instances of clock buffer 120 and conditional logic 110 in an integrated circuit may allow for fine grain power management.

Conditional logic 110 may be coupled to functional logic 105. Conditional logic 110 may monitor operation in functional logic 105 and/or other logic coupled to the functional logic 105 (not shown in FIG. 1). If conditional logic 110 detects that the functional logic 105 is idle, conditional logic 110 may assert a condition signal, which may be received by clock buffer circuit 120. In response to the asserted condition signal, the clock buffer circuit 120 may inhibit transitions of the output clock signal, Clk_out. Inhibiting the clock transitions of the output clock signal may result in reduced power consumption by the functional logic 105.

On the other hand, if the conditional logic 110 determines that the functional logic 105 is not idle, the conditional logic 110 deasserts the condition signal. The clock buffer circuit 120 may generate the clock signal Clk_out responsive to the deasserted condition signal.

Moving now to FIG. 2, a schematic diagram of one embodiment of clock buffer circuit 120 is shown. In the embodiment shown, clock buffer circuit 120 includes a pair of inverters for receiving the input clock signal (Clk). The inverters provide buffering for the Clk clock signal, producing the clock signal Clk_in. The inverters are optional buffering circuitry and may be eliminated in other embodiments. In some embodiments, clock buffer circuit 120 may be configured to produce Clk_in from an input clock signal Clk and a second clock signal having a 90° phase shift with respect to the input clock signal (referred to as quadrature clocks). In such embodiments, the clock signal Clk_in may be an exclusive OR of the clock signal Clk and the second clock signal and the clock signal Clk_in may be twice the frequency of the clock signal Clk.

Clock buffer circuit 120 also includes a condition input circuit for receiving a condition signal from conditional logic 110 comprising the transistors M7, M8, M9, and M10. The transistors M9 and M10 form a first passgate circuit coupled to receive the condition signal and coupled to the node N3. The transistors M7 and M8 form a second passgate circuit coupled between the node N3 and the node N2. The first passgate circuit is open during the low phase of the clock signal Clk_in and closed during the high phase of the clock signal Clk_in. The second passgate circuit is open during the high phase of the clock signal Clk_in and closed during the low phase of the clock signal Clk_in. In the embodiment shown, the condition signal is passed from the input to node N3 by the first passgate circuit responsive to the low phase of the clock signal. The condition signal is latched at node N3 responsive to the rising edge of the clock signal. The second passgate circuit may be used to feedback the voltage on the node N2 to the node N3 circuit in order to ensure stability of the node N3 during the high phase of the clock signal Clk_in.

The clock buffer circuit 120 as illustrated in FIG. 2 further includes an inverter Inv2 and the transistors M0, M1, M2, M3, M4, M5, and M6. Transistor M0 has a source terminal coupled to the voltage reference node (V_(dd)), a drain terminal coupled to the node N2, and a gate terminal coupled to receive the clock signal Clk_out. The inverter Inv2 is coupled between the node N2 and the node carrying the clock signal Clk_out. Transistor M1 has a source terminal coupled to the voltage reference node, a drain terminal coupled to the node N2, and a gate terminal coupled to receive the clock signal Clk_in. Transistor M2 has a source terminal coupled to the voltage reference node, a drain terminal coupled to the node N1, and a gate terminal coupled to receive the clock signal Clk_in. The transistor M3 has a source terminal coupled to the voltage reference node, a drain terminal coupled to the node N1, and a gate terminal coupled to the node N2. Transistor M4 has a drain terminal coupled to the node N2, a source terminal coupled to the node N4, and a gate terminal coupled to the node N1. Transistor M5 has a drain terminal coupled to the node N1, a source terminal coupled to the node N4, and a gate terminal coupled to the node N3. Transistor M6 has a drain terminal coupled to the node N4, a source terminal coupled to a ground reference node, and a gate terminal coupled to receive the clock signal Clk_in.

The transistors M1 and M2 may form a precharge circuit which precharges the nodes N1 and N2 during the low phase of the clock signal Clk_in. Since the node N2 is precharged, the clock signal Clk_out is also low responsive to the low phase of the clock signal Clk_in.

In response to an assertion of the condition signal (latched at node N3), transistor M5 is activated. Activating transistor M5 may effectively create a short circuit between the gate and source terminals of the transistor M4 (nodes N1 and N4), preventing a voltage drop across those terminals. Since the transistor M4 is deactivated, the node N2 is not drained and thus the clock signal Clk_out remains in a low state (the clock signal Clk_out is inhibited). A relatively short setup time may be supported, in one embodiment, for the condition signal. The condition signal setup time for assertion may depend on the amount of time elapsing from the assertion to the deactivation of transistor M4 through transistor M5 as compared to the amount of time from the rising edge of the clock signal Clk_in to the node N2 having significant charge drained through the combination of transistors M4 and M5.

The node N1 may be discharged through the combination of the transistors M5 and M6 in response to the high phase of the clock signal Clk_in and the condition signal being asserted. Discharging the node N1 may further ensure that the transistor M4 remains deactivated responsive to the asserted condition input signal. If the transistor M4 is deactivated, the stability of the voltage on the node N2 may be provided through the transistor M0. The transistor M0 may be optional and may be deleted in other embodiments.

In response to the condition signal being deasserted, the clock signal may propagate through the clock buffer circuit 120. In the embodiment shown, transistor M5 is deactivated when the condition signal is not asserted. Since the node N1 was precharged during the low phase of the clock, the transistor M4 may be activated. In response to the rising edge of the clock signal Clk_in, the transistor M6 is activated and the combination of transistor M4 and M6 may discharge the node N2. Discharging the node N2 causes the inverter Inv2 to charge the clock signal Clk_out, providing a rising edge on the clock signal Clk_out. The high phase of the clock signal Clk_out may continue until the transistor M1 precharges the node N2 in response to the low phase of the clock signal Clk_in. The discharging of the node N2 also activates the transistor M3, which may provide stability for the voltage on the node N1 since the transistors M2 and M5 are deactivated. Transistor M3 may be optional and may be deleted in other embodiments.

The setup time for the condition signal, according to one embodiment, may be further understood with regard to the signal on the node N4. The node N4 is precharged during the low phase of the clock signal Clk_in (by the transistor M1 through the transistor M4, and also by the transistor M2 through the transistor M5 if the condition signal is asserted during the precharge phase). The node N4 is discharged during the high phase of the clock through the transistor M6. Accordingly, the node N4 may track the clock signal Clk_in, 180° out of phase plus a relatively small delay.

If the condition signal is to be asserted, the setup time may be approximately coincident with the falling edge of the signal on the node N4. The condition signal may even assert somewhat later, as long as the output clock signal Clk_out is not glitched as a result. While the signal on the node N4 is at a high state, the transistor M4 is off (since there is not a positive gate-to-source voltage on the transistor M4). Thus, as long as the transistor M5 is activated at approximately the same time as the falling edge of the node N4 begins, maintaining the lack of a positive gate-to-source voltage on the transistor M4, the transistor M4 may remain deactivated and the rising edge of the clock signal Clk_out does not occur.

If the condition signal is to be deasserted, the setup time may again be approximately coincident with the falling edge of the signal on the node N4. In this case, the condition signal may be deasserted early enough to ensure that the transistor M5 does not activate in response to the falling edge of the signal on the node N4. Furthermore, if the condition signal is deasserted even later, the result may be only that the rising edge of the clock signal Clk_out is delayed.

In one particular implementation, the relative channel widths of various transistors (normalized to the channel width of M3) may be as follows:

M3: 1

M0: 2

M4: 4

M5: 12

M6: 12

Other implementations having different relative channel widths are possible and contemplated. Channel widths may also be varied based on the particular circuit configuration of alternate embodiments.

Turning now to FIG. 3, a timing diagram illustrating the operation of one embodiment of clock buffer circuit 120 of FIG. 2 is shown. Timing diagrams may be different for other embodiments (e.g. embodiments wherein quadrature clock signals are used to double the rate of the output clock). Clock buffer circuit 120 may receive an input clock signal, Clk, and produce an output clock signal, Clk_out, when the condition signal is de-asserted. The signal on the node N4 is also shown in FIG. 3. When the condition signal becomes asserted, clock buffer circuit 120 may respond by inhibiting transitions of the output clock signal. Inhibiting the clock signal for this embodiment may result in clock buffer circuit 120 preventing a positive-going transition of the output clock signal with the first rising edge of the input clock signal following assertion of the condition signal. Specifically, the condition signal is shown asserting in FIG. 3 approximately coincident with the falling edge of the signal on the node N4 (reference numeral 200). After the condition signal is de-asserted, the transitions of the output clock signal may then resume with the next rising edge of the input clock signal. The condition signal is shown deasserting in FIG. 3 approximately coincident with the falling edge of the signal on the node N4 (reference numeral 202).

It is noted that the shift in time between the clock signal Clk and the clock signal Clk_out may not be to scale with respect to the period of the clock signals. The period of time for the transitions of the signal on node N4 and the condition signal may be somewhat expanded to illustrate relationships therebetween.

Turning next to FIG. 4, a block diagram of a carrier medium 300 including one or more data structures representative of the clock buffer circuit 120 is shown. Generally speaking, a carrier medium may include storage media such as magnetic or optical media, e.g., disk or CD-ROM, volatile or non-volatile memory media such as RAM (e.g. SDRAM, RDRAM, SRAM, etc.), ROM, etc., as well as transmission media or signals such as electrical, electromagnetic, or digital signals, conveyed via a communication medium such as a network and/or a wireless link.

Generally, the data structure(s) of the clock buffer circuit 120 carried on carrier medium 300 may be read by a program and used, directly or indirectly, to fabricate the hardware comprising the processor 10. For example, the data structures may include one or more behavioral-level descriptions or register-transfer level (RTL) descriptions of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool which may synthesize the description to produce one or more netlists comprising a list of gates from a synthesis library. The netlist comprises a set of gates which also represent the functionality of the hardware comprising the clock buffer circuit 120. The netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor fabrication steps to produce a semiconductor circuit or circuits corresponding to the clock buffer circuit 120. Alternatively, the data structure(s) on carrier medium 300 may be the netlist(s) (with or without the synthesis library) or the data set(s), as desired.

While carrier medium 300 carries a representation of the clock buffer circuit 120, other embodiments may carry a representation of any portion of the clock buffer circuit 120 or circuitry including the clock buffer circuit, conditional logic and functional logic. Portions of the clock buffer circuit 120 may include any subset of the transistors shown in FIG. 4, etc.

It is noted that, while CMOS transistors have by used herein with a gate terminal which controls the electrical connection between source and drain terminals, other types of transistors may be used. Generally, a transistor may include at least three terminals, one of which is a control terminal for controlling the electrical connection between the other two terminals. For example, the gate terminal of a field effect transistor (such as a CMOS transistor) or the base terminal of a bi-polar junction transistor may be control terminals for those types of transistors.

While the present invention has been described with reference to particular embodiments, it will be understood that the embodiments are illustrative and that the invention scope is not so limited. Any variations, modifications, additions, and improvements to the embodiments described are possible. These variations, modifications, additions, and improvements may fall within the scope of the inventions as detailed within the following claims. 

What is claimed is:
 1. A clock buffer circuit comprising: a precharge circuit configured to precharge a first node; a first transistor having a first terminal coupled to the first node, a second terminal coupled to a second node, and a first control terminal; a second transistor having a third terminal coupled to the first control terminal, a fourth terminal coupled to the second node, and a second control terminal coupled to receive a condition signal; and a third transistor having a fifth terminal coupled to the second node, a sixth terminal, and a third control terminal coupled to receive a clock signal; wherein the second transistor is activated responsive to the condition signal, and wherein the third transistor is configured to discharge the second node responsive to an assertion of the clock signal, and wherein a setup time of the condition signal to the second transistor is determined by a falling edge of a signal on the second node.
 2. The clock buffer circuit as recited in claim 1 wherein the setup time is approximately coincident with the falling edge.
 3. The clock buffer circuit as recited in claim 1 wherein the setup time is negative with respect to the falling edge.
 4. The clock buffer circuit as recited in claim 1 wherein the first control terminal and the third terminal form a third node, and wherein the precharge circuit is further configured to precharge the third node.
 5. The clock buffer circuit as recited in claim 4, wherein the second node is precharged through the first transistor during use.
 6. The clock buffer circuit as recited in claim 4, wherein the precharge circuit includes a fourth transistor and a fifth transistor coupled to the first node and the third node, respectively, and having control terminals coupled to receive the clock signal.
 7. A carrier medium comprising one or more data structures read by a program during an integrated circuit fabrication process, the one or more data structures representing: a precharge circuit configured to precharge a first node; a first transistor having a first terminal coupled to the first node, a second terminal coupled to a second node, and a first control terminal; a second transistor having a third terminal coupled to the first control terminal, a fourth terminal coupled to the second node, and a second control terminal coupled to receive a condition signal; and a third transistor having a fifth terminal coupled to the second node, a sixth terminal, and a third control terminal coupled to receive a clock signal; wherein the second transistor is activated responsive to the condition signal, and wherein the third transistor is configured to discharge the second node responsive to an assertion of the clock signal, and wherein a setup time of the condition signal to the second transistor is determined by a falling edge of a signal on the second node.
 8. The carrier medium as recited in claim 7 wherein the setup time is approximately coincident with the falling edge.
 9. The carrier medium as recited in claim 7 wherein the setup time is negative with respect to the falling edge.
 10. The carrier medium as recited in claim 7 wherein the first control terminal and the third terminal form a third node, and wherein the precharge circuit is further configured to precharge the third node.
 11. The carrier medium as recited in claim 10, wherein the second node is precharged through the first transistor during use.
 12. The carrier medium as recited in claim 10, wherein the precharge circuit includes a fourth transistor and a fifth transistor coupled to the first node and the third node, respectively, and having control terminals coupled to receive the clock signal.
 13. An integrated circuit comprising: a functional logic unit; a conditional logic unit coupled to the functional logic unit, the conditional logic unit configured to produce a condition signal; and a clock buffer circuit coupled to the conditional logic unit and configure to drive an output clock signal to the functional logic unit, the conditional clock buffer circuit comprising: a precharge circuit configured to precharge a first node; a first transistor having a first terminal coupled to the first node, a second terminal coupled to a second node, and a first control terminal; a second transistor having a third terminal coupled to the first control terminal, a fourth terminal coupled to the second node, and a second control terminal coupled to receive a condition signal; and a third transistor having a fifth terminal coupled to the second node, a sixth terminal, and a third control terminal coupled to receive a clock signal; wherein the second transistor is activated responsive to the condition signal, and wherein the third transistor is configured to discharge the second node responsive to an assertion of the clock signal, and wherein a setup time of the condition signal to the second transistor is determined by a falling edge of a signal on the second node.
 14. The integrated circuit as recited in claim 13 wherein the clock buffer circuit further comprises an output circuit coupled to the first node and configured to drive the output clock signal.
 15. The integrated circuit as recited in claim 13 wherein the setup time is approximately coincident with the falling edge.
 16. The integrated circuit as recited in claim 13 wherein the setup time is negative with respect to the falling edge.
 17. The integrated circuit as recited in claim 13 wherein the first control terminal and the third terminal form a third node, and wherein the precharge circuit is further configured to precharge the third node.
 18. The integrated circuit as recited in claim 17, wherein the second node is precharged through the first transistor during use.
 19. The integrated circuit as recited in claim 17, wherein the precharge circuit includes a fourth transistor and a fifth transistor coupled to the first node and the third node, respectively, and having control terminals coupled to receive the clock signal. 